Internships/ProjectIdeas/AVX: Difference between revisions
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=== AVX === | === AVX === | ||
'''Status:''' Jan Bobek is working on this project for GSoC. | |||
'''Summary:''' Support for AVX within TCG | '''Summary:''' Support for AVX within TCG | ||
The target/i386 front end has support for TCG emulation of SSE4.1, but does not have support for later vector extensions such as AVX. | QEMU's TCG just-in-time compiler translates target CPU instructions into host CPU instructions so that programs written for other CPU architectures can be run on any host. Modern CPUs features vector processing instruction sets, sometimes called Single Instruction Multiple Data (SIMD) instructions, for performing the same operation on multiple elements of data in just one instruction. Intel's SSE and AVX instruction set extensions were introduced for x86 CPUs for this purpose. | ||
The target/i386 front end has support for TCG emulation of SSE4.1, but does not have support for later vector extensions such as AVX. Your task is to implement and test AVX instructions that are currently missing in QEMU. | |||
'''Links:''' | '''Links:''' | ||
* http://lists.nongnu.org/archive/html/qemu-devel/2018-12/msg06250.html | |||
* https://en.wikipedia.org/wiki/Advanced_Vector_Extensions | |||
'''Details:''' | '''Details:''' | ||
* Skill level: intermediate to advanced | |||
* Language: C | |||
* Mentor: Richard Henderson <richard.henderson@linaro.org> (rth on #qemu IRC) | |||
* Suggested by: Nick Renieris | |||
Latest revision as of 15:16, 17 May 2019
AVX
Status: Jan Bobek is working on this project for GSoC.
Summary: Support for AVX within TCG
QEMU's TCG just-in-time compiler translates target CPU instructions into host CPU instructions so that programs written for other CPU architectures can be run on any host. Modern CPUs features vector processing instruction sets, sometimes called Single Instruction Multiple Data (SIMD) instructions, for performing the same operation on multiple elements of data in just one instruction. Intel's SSE and AVX instruction set extensions were introduced for x86 CPUs for this purpose.
The target/i386 front end has support for TCG emulation of SSE4.1, but does not have support for later vector extensions such as AVX. Your task is to implement and test AVX instructions that are currently missing in QEMU.
Links:
- http://lists.nongnu.org/archive/html/qemu-devel/2018-12/msg06250.html
- https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
Details:
- Skill level: intermediate to advanced
- Language: C
- Mentor: Richard Henderson <richard.henderson@linaro.org> (rth on #qemu IRC)
- Suggested by: Nick Renieris