ChangeLog/7.2: Difference between revisions
(→RISC-V) |
|||
Line 43: | Line 43: | ||
=== RISC-V === | === RISC-V === | ||
==== ISA and Extensions ==== | ==== ISA and Extensions ==== | ||
* Update [m|h]tinst CSR in interrupt handling | |||
* Force disable extensions if priv spec version does not match | |||
* fix shifts shamt value for rv128c | |||
* move zmmul out of the experimental | |||
* Add checks for supported extension combinations | |||
* Fix typo and restore Pointer Masking functionality for RISC-V | |||
* Add mask agnostic behaviour (rvv_ma_all_1s) for vector extension | |||
* Add Zihintpause support | |||
* Add xicondops in ISA entry | |||
* Use official extension names for AIA CSRs | |||
==== Machines ==== | ==== Machines ==== | ||
* virt: pass random seed to fdt | |||
* opentitan: bump opentitan version | |||
* virt machine device tree improvements | |||
==== Fixes and Misc ==== | ==== Fixes and Misc ==== | ||
* Upgrade OpenSBI to v1.1 | |||
* microchip_pfsoc: fix kernel panics due to missing peripherals | |||
* Remove additional priv version check for mcountinhibit | |||
=== s390x === | === s390x === |
Revision as of 08:11, 8 September 2022
System emulation
Incompatible changes
Consult the 'Removed features' page for details of suggested replacement functionality.
New deprecated options and features
Consult the "Deprecated Features" chapter of the QEMU System Emulation User's Guide for further details of the deprecations and their suggested replacements.
68k
Alpha
Arm
Machines
AVR
Hexagon
HPPA
LoongArch
Microblaze
MIPS
Nios2
OpenRISC
- Stability improvements
- Performance improvements by supporting MTTCG
- New virt platform is added to assist with CI and device testing
PowerPC
Renesas RX
Renesas SH
RISC-V
ISA and Extensions
- Update [m|h]tinst CSR in interrupt handling
- Force disable extensions if priv spec version does not match
- fix shifts shamt value for rv128c
- move zmmul out of the experimental
- Add checks for supported extension combinations
- Fix typo and restore Pointer Masking functionality for RISC-V
- Add mask agnostic behaviour (rvv_ma_all_1s) for vector extension
- Add Zihintpause support
- Add xicondops in ISA entry
- Use official extension names for AIA CSRs
Machines
- virt: pass random seed to fdt
- opentitan: bump opentitan version
- virt machine device tree improvements
Fixes and Misc
- Upgrade OpenSBI to v1.1
- microchip_pfsoc: fix kernel panics due to missing peripherals
- Remove additional priv version check for mcountinhibit
s390x
SPARC
Tricore
x86
Xtensa
Device emulation and assignment
ACPI / SMBIOS
Audio
Block devices
Graphics
I2C
Controllers
Devices
Input devices
IPMI
Multi-process QEMU
Network devices
NVDIMM
NVMe
Emulated NVMe Controller
PCI/PCIe
SCSI
SD card
SMBIOS
TPM
USB
VFIO
virtio
Xen
fw_cfg
9pfs
virtiofs
Semihosting
Audio
Character devices
- UNIX socket support on Windows has been added
Crypto subsystem
Authorization subsystem
GUI
GDBStub
TCG Plugins
Host support
Memory backends
Migration
Monitor
QMP
HMP
Network
Block device backends and tools
Tracing
Semihosting
Miscellaneous
User-mode emulation
build
binfmt_misc
Hexagon
LoongArch
Nios2
HPPA
TCG
ARM
Guest agent
Build Information
Python
GIT submodules
Container Based Builds
VM Based Builds
Build Dependencies
- Python 3.7 or newer is now required.
Windows
Testing and CI
Known issues
- see Planning/7.2