Features/Xtensa: Difference between revisions
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== Summary == | == Summary == | ||
Add emulation of the Tensilica Xtensa processor family. | Add emulation of the [http://en.wikipedia.org/wiki/Tensilica Tensilica Xtensa] processor family. | ||
== Owner == | == Owner == | ||
Revision as of 11:40, 10 October 2011
Summary
Add emulation of the Tensilica Xtensa processor family.
Owner
- Name: Max Filippov / Open Source and Linux Lab
- Email: jcmvbkbc@gmail.com
Status
Target can run linux on sim and lx60 boards with dc232b cpu. Kernel must be loaded with -kernel option, rootfs may be in a filesystem image file for the sim board, or may be mounted via NFS for the lx60.
Target configured with custom cpu can run ThreadX RTOS.
Support for new cpu cores may be added with minimal amount of hand-written code by reusing architecture variant overlay.
TODO
- implement remaining hardware for the lx60 board (FLASH, LEDs, DIP switches, LCD?, audio codec?);
- implement remaining core ISA options: coprocessors, floating point, debug and cache;
- implement cycle-accurate simulation mode;
- implement ISA extensions like FLIX, wide branches or SIMD;
- implement interrupt distribution hardware for SMP configurations;
Development
Current development status, useful links and related repos may be found there: http://wiki.osll.spb.ru/doku.php?id=etc:users:jcmvbkbc:qemu-target-xtensa