Features/QOM/CPU: Difference between revisions
(Update status with new qom-cpu-dev branch) |
(Add OMAP5 to list of mixed-core SoCs) |
||
| Line 14: | Line 14: | ||
#* ARM big.LITTLE: Cortex-A15 + Cortex-A7 | #* ARM big.LITTLE: Cortex-A15 + Cortex-A7 | ||
#* Freescale Vybrid VF6xx/VF7xx: Cortex-A5 + Cortex-M4 | #* Freescale Vybrid VF6xx/VF7xx: Cortex-A5 + Cortex-M4 | ||
#* TI OMAP5: Cortex-A15 + Cortex-M4 | |||
# Long-term: Work towards allowing to compile multiple targets into one executable. | # Long-term: Work towards allowing to compile multiple targets into one executable. | ||
#* Renesas R-Car H1, M1A: ARM Cortex-A9 + SH-4A | #* Renesas R-Car H1, M1A: ARM Cortex-A9 + SH-4A | ||
Revision as of 23:08, 14 June 2012
Summary
Convert CPUState to QOM.
Motivation
- Short-term: Allow inspecting and modifying CPU properties via QOM.
- Short-term: Avoid common target code doing ifs or switches on CPU identifiers.
- target-arm/helper.c: cpu_reset_model_id()
- Short-term: Replace CPU_COMMON macro and duplicated reset code by inheritance.
- Mid-term: Avoid dependency of common code on #defines from cpu.h.
- Mid-term: Ease instantiation of mixed software-visible cores within one target, e.g.
- NXP LPC43xx: Cortex-M4 + Cortex-M0
- ARM big.LITTLE: Cortex-A15 + Cortex-A7
- Freescale Vybrid VF6xx/VF7xx: Cortex-A5 + Cortex-M4
- TI OMAP5: Cortex-A15 + Cortex-M4
- Long-term: Work towards allowing to compile multiple targets into one executable.
- Renesas R-Car H1, M1A: ARM Cortex-A9 + SH-4A
- Renesas R-Home S1: ARM Cortex-A9 + SH-4A + ARM7TDMI-S
"CPU" name conflict
| Identifier | current | interim | final |
|---|---|---|---|
| struct CPU$archState or struct CPUState_$arch |
defined in target-*/cpu.h | ??? | |
| #define CPUState | alias to CPU$archState / CPUState_$arch | dropped in favor of CPU | |
| struct CPUClass | class | ||
| #define CPU_CLASS(class) | cast macro for class | ||
| struct CPU | object | ||
| #define CPU(obj) | cast macro for object | ||
| #define CPU_GET_CLASS(obj) | macro to obtain class pointer | ||
Resolved by renaming existing CPUState to CPUArchState and by using struct CPUState for the object state, while using CPU(obj) as macro for casting.
Owner
- Name: Andreas Färber
- Email: afaerber@suse.de
Status
QOM CPUState exists, former CPUState is renamed to CPUArchState. All targets have been converted for v1.1-rc0.
Initial field movements from CPUArchState to CPUState and subsequent signature adaptations are on the list.
TLB redesign is still open - suggestions welcome.
Patch series and branches
NB: Due to hosting issues, branches have moved to GitHub.
| name | depends on |
|---|---|
| qom-1.1 | |
| qom-cpu-1.1 (cleanups) | |
| qom-next | |
| qom-cpu-x86, part 3 (classes) | |
| qom-cpu-sh4, part 2 | |
| qom-cpu-unicore32, part 2 | |
| qom-cpu-alpha, part 2 | |
| qom-cpu, part 4 (common) | qom-next |
| qom-cpu, part 5 (device) | qom-next |