ChangeLog/7.1

System emulation

Incompatible changes

Consult the 'Removed features' page for details of suggested replacement functionality

New deprecated options and features

Consult the "Deprecated Features" chapter of the QEMU System Emulation User's Guide for further details of the deprecations and their suggested replacements.

Arm

• The xlnx-zynqmp SoC model now implements the 4 TTC timers
• The versal machine now models the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
• The virt board now supports emulation of the GICv4.0

Nios2

• Implement the Vectored Interrupt Controller (enable with -machine 10m50-ghrd,vic=on).
• Implement shadow register sets, and enable them with the VIC.
• Raise supervisor-only instruction exception for ERET and BRET.
• Raise misaligned data exception for misaligned memory accesses.
• Raise misaligned destination exception for misaligned branch addresses.
• Raise division error exception for divide by zero and divide overflow (disable with -cpu diverr_present=off).

Renesas RX

• Fix the clrpsw and setpsw instructions with respect to changes to PSW.U.
• Fix the wait instruction corrupting the PC and setting PSW.I.

RISC-V

• Add support for Ibex SPI to OpenTitan
• Add support for privileged spec version 1.12.0
• Use privileged spec version 1.12.0 for virt machine by default
• Allow software access to MIP SEIP
• Add initial support for the Sdtrig extension
• Optimisations for vector extensions
• Improvements to the misa ISA string
• Add isa extenstion strings to the device tree
• Don't allow `-bios` options with KVM machines
• Fix NAPOT range computation overflow
• Fix DT property mmu-type when CPU mmu option is disabled
• Make RISC-V ACLINT mtime MMIO register writable
• Add and enable native debug feature
• Support 64bit fdt addresses

s390x

• Fix condition code generation for the ICMH instruction.

User-mode emulation

Nios2

• Fix the rt_sigreturn system call.
• Fix the siginfo_t data for SIGSEGV.

Known issues

• see Planning/7.1