Documentation/ISAManuals: Difference between revisions
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= Instruction Set Manuals = | = Instruction Set Manuals = | ||
Some pointers for the various ISAs that QEMU supports. | Some pointers for the various ISAs that QEMU supports (either as target or as host). | ||
* [http://en.wikibooks.org/wiki/Subject:Assembly_languages Wikibooks (Various languages)] | * [http://en.wikibooks.org/wiki/Subject:Assembly_languages Wikibooks (Various languages)] | ||
== Alpha == | |||
* [http://h18002.www1.hp.com/alphaserver/technology/chip-docs.html Alpha] (look for the "Alpha Architecture Handbook") | |||
== ARM == | == ARM == | ||
* [ | * [https://developer.arm.com/products/architecture/a-profile/docs List of A-profile related documentation] | ||
* [https://developer.arm.com/products/architecture/m-profile/docs List of M-profile related documentation] | |||
* The most significant document is the [https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile v8A ARM ARM] | |||
If you are spending time in the translator or generator you may find the [https://developer.arm.com/products/architecture/a-profile/exploration-tools HTML rendering of the XML] more useful. | |||
== Blackfin == | == Blackfin == | ||
* [http://www.analog.com/static/imported-files/processor_manuals/ | * [http://www.analog.com/static/imported-files/processor_manuals/Blackfin_pgr_rev2.0.pdf Blackfin] | ||
== CRIS == | |||
== HPPA (PA-RISC) == | |||
* [https://parisc.wiki.kernel.org/images-parisc/6/68/Pa11_acd.pdf PA-RISC 1.1 (32bit) Instruction Set Architecture] | |||
* [https://parisc.wiki.kernel.org/images-parisc/7/73/Parisc2.0.pdf PA-RISC 2.0 (64bit) Instruction Set Architecture] | |||
== LatticeMico32 == | |||
* [http://www.latticesemi.com/documents/doc41986x74.pdf LatticeMico32] | |||
== m68k == | |||
* [http://www.nxp.com/files/archives/doc/ref_manual/M68000PRM.pdf M68k Programmer's Reference Manual] | |||
* [http://www.nxp.com/files/dsp/doc/ref_manual/CFPRM.pdf ColdFire Programmer's Reference Manual] | |||
== Microblaze == | |||
== MIPS == | |||
* [http://www.mips.com/products/product-materials/processor/mips-architecture/ MIPS32 and MIPS64] | |||
== PowerPC == | == PowerPC == | ||
* [http://www.ibm.com/developerworks/systems/library/es-archguide-v2.html PowerPC 2.02] | * [http://www.ibm.com/developerworks/systems/library/es-archguide-v2.html PowerPC 2.02] | ||
* [ | * [https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b PowerISA 2.07 (POWER8) ] | ||
* [https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0 PowerISA 3.0 (POWER9) ] | |||
== S390x (zSeries) == | == S390x (zSeries) == | ||
* [http://lars.nocrew.org/computers/processors/ESA390/dz9zr002.pdf | * [http://lars.nocrew.org/computers/processors/ESA390/dz9zr002.pdf z/Architecture Principles of Operation] (Third edition, 2003) | ||
* [http://www-01.ibm.com/support/docview.wss?uid=isg26480faec85f44e2385256d5200627dee&aid=1 z/Architecture Principles of Operation] (Fourth edition, 2004) | |||
* [http://publibfp.dhe.ibm.com/epubs/pdf/dz9zr009.pdf z/Architecture Principles of Operation] (Tenth edition, 2012) | |||
* [https://www-304.ibm.com/support/docview.wss?uid=isg29c69415c1e82603c852576700058075a&aid=1 z/Architecture Reference Summary] (Ninth edition, 2015) | |||
* [http://bitsavers.trailing-edge.com/pdf/ibm/370/princOps/SA22-7095-0_370-XA_Interpretive_Execution_Jan84.pdf s370 Interpretive Execution] | |||
== SH4 == | |||
== SPARC == | |||
* [http://www.sparc.org/specificationsDocuments.html SPARC v8 and v9] | |||
== TriCore == | |||
=== v1.3 & v1.3.1 === | |||
* [https://www.infineon.com/dgdl/tc_v131_corearchitecture_v__138.pdf?fileId=db3a304412b407950112b409c4500359 Volume 1] | |||
* [http://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=db3a304412b407950112b409b6dd0352 Volume 2] | |||
=== v1.6 === | |||
* [https://www.infineon.com/dgdl/tc1_6__architecture_vol1.pdf?fileId=db3a3043372d5cc801373b0f374d5d67 Volume 1] | |||
* [http://www.infineon.com/dgdl/tc1_6__architecture_vol2.pdf?fileId=db3a3043372d5cc801374ad9c0653ad9 Volume 2] | |||
=== v1.6.1 (aka 1.6P/E) === | |||
* [https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol1-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bea3624a5 Volume 1] | |||
* [https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bf33124a8 Volume 2] | |||
=== 1.6.2 === | |||
* [https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd Volume 1] | |||
* [https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 Volume 2] | |||
== x86 == | == x86 == | ||
* [http://developer.amd.com/documentation/guides/pages/default.aspx AMD] | * [http://developer.amd.com/documentation/guides/pages/default.aspx AMD] | ||
* [http://www.intel.com/products/processor/manuals/ Intel] | |||
== Xtensa == | |||
* [https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/tensilica-ip/isa-summary.pdf Base Xtensa ISA] | |||
Latest revision as of 13:24, 19 May 2023
Instruction Set Manuals
Some pointers for the various ISAs that QEMU supports (either as target or as host).
Alpha
- Alpha (look for the "Alpha Architecture Handbook")
ARM
- List of A-profile related documentation
- List of M-profile related documentation
- The most significant document is the v8A ARM ARM
If you are spending time in the translator or generator you may find the HTML rendering of the XML more useful.
Blackfin
CRIS
HPPA (PA-RISC)
LatticeMico32
m68k
Microblaze
MIPS
PowerPC
S390x (zSeries)
- z/Architecture Principles of Operation (Third edition, 2003)
- z/Architecture Principles of Operation (Fourth edition, 2004)
- z/Architecture Principles of Operation (Tenth edition, 2012)
- z/Architecture Reference Summary (Ninth edition, 2015)
- s370 Interpretive Execution