Features/QOM/CPU: Difference between revisions

From QEMU
(Update status with new qom-cpu-dev branch)
(Add OMAP5 to list of mixed-core SoCs)
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#* ARM big.LITTLE: Cortex-A15 + Cortex-A7
#* ARM big.LITTLE: Cortex-A15 + Cortex-A7
#* Freescale Vybrid VF6xx/VF7xx: Cortex-A5 + Cortex-M4
#* Freescale Vybrid VF6xx/VF7xx: Cortex-A5 + Cortex-M4
#* TI OMAP5: Cortex-A15 + Cortex-M4
# Long-term: Work towards allowing to compile multiple targets into one executable.
# Long-term: Work towards allowing to compile multiple targets into one executable.
#* Renesas R-Car H1, M1A: ARM Cortex-A9 + SH-4A
#* Renesas R-Car H1, M1A: ARM Cortex-A9 + SH-4A

Revision as of 23:08, 14 June 2012

Summary

Convert CPUState to QOM.

Motivation

  1. Short-term: Allow inspecting and modifying CPU properties via QOM.
  2. Short-term: Avoid common target code doing ifs or switches on CPU identifiers.
    • target-arm/helper.c: cpu_reset_model_id()
  3. Short-term: Replace CPU_COMMON macro and duplicated reset code by inheritance.
  4. Mid-term: Avoid dependency of common code on #defines from cpu.h.
  5. Mid-term: Ease instantiation of mixed software-visible cores within one target, e.g.
    • NXP LPC43xx: Cortex-M4 + Cortex-M0
    • ARM big.LITTLE: Cortex-A15 + Cortex-A7
    • Freescale Vybrid VF6xx/VF7xx: Cortex-A5 + Cortex-M4
    • TI OMAP5: Cortex-A15 + Cortex-M4
  6. Long-term: Work towards allowing to compile multiple targets into one executable.
    • Renesas R-Car H1, M1A: ARM Cortex-A9 + SH-4A
    • Renesas R-Home S1: ARM Cortex-A9 + SH-4A + ARM7TDMI-S

"CPU" name conflict

Identifier current interim final
struct CPU$archState or
struct CPUState_$arch
defined in target-*/cpu.h ???
#define CPUState alias to CPU$archState / CPUState_$arch dropped in favor of CPU
struct CPUClass class
#define CPU_CLASS(class) cast macro for class
struct CPU object
#define CPU(obj) cast macro for object
#define CPU_GET_CLASS(obj) macro to obtain class pointer

Resolved by renaming existing CPUState to CPUArchState and by using struct CPUState for the object state, while using CPU(obj) as macro for casting.

Owner

  • Name: Andreas Färber
  • Email: afaerber@suse.de

Status

QOM CPUState exists, former CPUState is renamed to CPUArchState. All targets have been converted for v1.1-rc0.

Initial field movements from CPUArchState to CPUState and subsequent signature adaptations are on the list.

TLB redesign is still open - suggestions welcome.

Patch series and branches

NB: Due to hosting issues, branches have moved to GitHub.

name depends on
type_init()
qom-user type_init()
object_class_get_list()
qom-cpu qom-user
qom-cpu-arm qom-cpu
qom-cpu-unicore32 qom-cpu
qom-cpu-s390 qom-cpu
qom-cpu-x86, part 1 qom-cpu
qom-cpu-sparc qom-cpu, qom-cpu-s390
qom-cpu-ppc qom-cpu
qom-cpu-alpha qom-cpu, qom-cpu-unicore32
qom-cpu-lm32 qom-cpu, qom-cpu-arm, qom-cpu-s390
qom-cpu-xtensa qom-cpu, qom-cpu-unicore32, qom-cpu-alpha
qom-cpu-cris qom-cpu, qom-cpu-arm, qom-cpu-s390, qom-cpu-lm32
qom-cpu-microblaze qom-cpu, qom-cpu-arm, qom-cpu-s390, qom-cpu-lm32, qom-cpu-cris
qom-cpu-sh4, part 1 qom-cpu, qom-cpu-s390, qom-cpu-sparc, qom-cpu-lm32, qom-cpu-microblaze
qom-cpu-m68k qom-cpu, object_class_get_list(), qom-cpu-arm, qom-cpu-s390, qom-cpu-lm32, qom-cpu-cris, qom-cpu-microblaze, qom-cpu-sh4
qom-cpu-mips qom-cpu, qom-cpu-s390, qom-cpu-lm32, qom-cpu-microblaze, qom-cpu-sh4, qom-cpu-m68k
qom-cpu, part 2 (cleanup) qom-cpu-arm, qom-cpu-unicore32, qom-cpu-s390, qom-cpu-x86, qom-cpu-sparc, qom-cpu-ppc, qom-cpu-alpha, qom-cpu-lm32, qom-cpu-xtensa, qom-cpu-cris, qom-cpu-microblaze, qom-cpu-sh4, qom-cpu-m68k, qom-cpu-mips
qom-cpu-x86, part 2 (props)
qom-1.1
qom-cpu-1.1 (cleanups)
qom-next
qom-cpu, part 3 (reset) qom-cpu-1.1
qom-cpu-x86, part 3 (classes)
qom-cpu-sh4, part 2
qom-cpu-unicore32, part 2
qom-cpu-alpha, part 2
qom-cpu-arm, part 2 (followups to qom-cpu part 3 and cherry-picks from part 4) qom-cpu-reset
qom-cpu, part 4 (common) qom-next
qom-cpu, part 5 (device) qom-next