Documentation/ISAManuals: Difference between revisions

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== HPPA (PA-RISC) ==
== HPPA (PA-RISC) ==


* [http://h21007.www2.hp.com/dspp/tech/tech_TechByTypePage_IDX/1,4690,40106-0,00.html HPPA] (search for "PA-RISC Architecture")
* [https://parisc.wiki.kernel.org/images-parisc/6/68/Pa11_acd.pdf PA-RISC 1.1 (32bit) Instruction Set Architecture]
* [https://parisc.wiki.kernel.org/images-parisc/7/73/Parisc2.0.pdf PA-RISC 2.0 (64bit) Instruction Set Architecture]


== LatticeMico32 ==
== LatticeMico32 ==
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== TriCore ==
== TriCore ==
* [http://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=db3a304412b407950112b409b6dd0352 TriCore v1.3 & v1.3.1]
=== v1.3 & v1.3.1 ===
* [http://www.infineon.com/dgdl/tc1_6__architecture_vol2.pdf?fileId=db3a3043372d5cc801374ad9c0653ad9 TriCore v1.6]
* [https://www.infineon.com/dgdl/tc_v131_corearchitecture_v__138.pdf?fileId=db3a304412b407950112b409c4500359 Volume 1]
* [http://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=db3a304412b407950112b409b6dd0352 Volume 2]
=== v1.6 ===
* [https://www.infineon.com/dgdl/tc1_6__architecture_vol1.pdf?fileId=db3a3043372d5cc801373b0f374d5d67 Volume 1]
* [http://www.infineon.com/dgdl/tc1_6__architecture_vol2.pdf?fileId=db3a3043372d5cc801374ad9c0653ad9 Volume 2]
 
=== v1.6.1 (aka 1.6P/E) ===
* [https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol1-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bea3624a5 Volume 1]
* [https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bf33124a8 Volume 2]
=== 1.6.2 ===
* [https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd Volume 1]
* [https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 Volume 2]
 
== x86 ==
== x86 ==


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== Xtensa ==
== Xtensa ==


* [http://www.tensilica.com/uploads/file/747/88/ISA_Reference_Manual.pdf Xtensa] (you'll need to register an account)
* [https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/tensilica-ip/isa-summary.pdf Base Xtensa ISA]

Latest revision as of 13:24, 19 May 2023

Instruction Set Manuals

Some pointers for the various ISAs that QEMU supports (either as target or as host).

Alpha

  • Alpha (look for the "Alpha Architecture Handbook")

ARM

If you are spending time in the translator or generator you may find the HTML rendering of the XML more useful.

Blackfin

CRIS

HPPA (PA-RISC)

LatticeMico32

m68k

Microblaze

MIPS

PowerPC

S390x (zSeries)

SH4

SPARC

TriCore

v1.3 & v1.3.1

v1.6

v1.6.1 (aka 1.6P/E)

1.6.2

x86

Xtensa