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PCI Express Root Port enhancements

Summary: Add PCI Express advanced features to QEMU's emulated PCI Express Root Ports

QEMU's PCI Express machine (Q35) emulates generic PCI Express Root Ports.

The PCI Express Root Port emulation today supports only a subset of PCI Express advanced capabilities, missing several ones that could add a lot of functionality and make it closer to real hardware.

The goal of this summer project is to improve the PCI Express Root Port implementation by:

  1. Exposing the Root Port as PCIe Gen3. This requires tweaking the PCIe Root Port configuration registers to report link capabilities advertising Gen3 speeds/widths.
  2. Supporting up to 256 PCI Devices. This requires implementing the Alternative Routing-ID Interpretation (ARI) capability for the PCI Express Root Port. A PCI function can be located in Configuration Space by a <bus,dev,func> tuple. The 'func' part is 3 bits wide, meaning a multi-function device can have up to 8 functions. Since PCI Express architecture dictates only one device per PCIe bus, ARI uses a <bus,func> address, this time 'func' using 8 bits resulting in 256 functions per PCI device.
  3. Securing PCI Express devices via the Access Control Services (ACS) mechanism. ACS can force Peer-to-Peer PCIe transactions to go up through the PCIe Root Complex. ACS can be thought of as a kind of gate-keeper - preventing unauthorized transactions from occurring. For example without ACS, several multi-function PCIe Root Ports belonging to the same slot cannot be used with the vIOMMU for nested virtualization since they can "talk" to each other bypassing it.



  • Skill level: intermediate
  • Language: C
  • Mentor:, marcel_a on IRC
  • Suggested by: Marcel Apfelbaum <>