Internships/ProjectIdeas/RISCVVectorFrontendOptimization

RISC-V Vector TCG Frontend Optimization

Summary: Improve QEMU's performance on RISC-V vector instructions.

The RISC-V vector extension has been implemented in QEMU, but we have some performance pathologies mapping it to existing TCG backends. This project aims to improve the performance of the RISC-V vector ISA's mappings to QEMU TCG just-in-time compiler.

The RISC-V TCG frontend (ie, decoding RISC-V instructions and emitting TCG calls to emulate them) has some inefficient mappings to TCG, which results in binaries that have vector instructions frequently performing worse than those without, sometimes even up to 10x slower. This causes various headaches for users, including running toolchain regressions and doing distro work. This project's aim would be to bring the performance of vectorized RISC-V code to a similar level as the corresponding scalar code.

This will definitely require changing the RISC-V TCG frontend. It's likely there is some remaining optimization work that can be done without adding TCG primitives, but it may be necessary to do some core TCG work in order to improve performance sufficiently.

Internship tasks:

TODO

Links:

Details

Project size: 350 hours
Skill level: intermediate
Language: C, RISC-V assembly
Mentors: Palmer Dabbelt <palmer@dabbelt.com>