Features/Xtensa: Difference between revisions

Latest revision as of 21:25, 10 August 2024

Summary

Add emulation of the Tensilica Xtensa processor family.

Owner

Name: Max Filippov / Open Source and Linux Lab
Email: jcmvbkbc@gmail.com

Status

Target can run linux on sim and xtfpga (lx60/lx200/ml605/kc705) boards with dc232b/dc233c/fsf/custom cpus in system and linux-user emulation modes. Kernel may be loaded with -kernel option, or by u-boot from FLASH or from TFTP, rootfs may be in a filesystem image file for the sim board, or may be mounted via NFS for the xtfpga.

Support for new cpu cores may be added automatically by reusing architecture variant overlay, but only core ISA instructions are supported.

xtensa softmmu QEMU is used in several projects:

TODO

implement TIE support;
implement remaining hardware for xtfpga boards (LEDs, DIP switches, LCD?, audio codec?);

Development

Current development status, useful links and related repos may be found there: http://wiki.osll.ru/doku.php?id=etc:users:jcmvbkbc:qemu-target-xtensa

Linux/xtensa page about Xtensa on QEMU.

@@ Line 10: / Line 10: @@
 == Status ==
-Target can run linux on sim and lx60 boards with dc232b cpu. Kernel must be loaded with -kernel option, rootfs may be in a filesystem image file for the sim board, or may be mounted via NFS for the lx60.
+Target can run linux on sim and xtfpga (lx60/lx200/ml605/kc705) boards with dc232b/dc233c/fsf/custom cpus in system and linux-user emulation modes. Kernel may be loaded with -kernel option, or by u-boot from FLASH or from TFTP, rootfs may be in a filesystem image file for the sim board, or may be mounted via NFS for the xtfpga.
-Target configured with custom cpu can run ThreadX RTOS.
+Support for new cpu cores may be added automatically by reusing architecture variant overlay, but only core ISA instructions are supported.
-Support for new cpu cores may be added with minimal amount of hand-written code by reusing architecture variant overlay.
+xtensa softmmu QEMU is used in several projects:
+* [http://docs.zephyrproject.org/boards/xtensa/qemu_xtensa/doc/board.html Zephyr OS]
+* [https://www.alsa-project.org/main/index.php/Firmware#Using_the_Qemu_DSP_emulator Sound Open Firmware for Intel Baytrail chips]
 == TODO ==
-* implement remaining hardware for the lx60 board (FLASH, LEDs, DIP switches, LCD?, audio codec?);
+* implement TIE support;
-* implement remaining core ISA options: coprocessors, floating point, debug and cache;
+* implement remaining hardware for xtfpga boards (LEDs, DIP switches, LCD?, audio codec?);
-* implement cycle-accurate simulation mode;
-* implement ISA extensions like FLIX, wide branches or SIMD;
-* implement interrupt distribution hardware for SMP configurations;
 == Development ==
-Current development status, useful links and related repos may be found there: http://wiki.osll.spb.ru/doku.php?id=etc:users:jcmvbkbc:qemu-target-xtensa
+Current development status, useful links and related repos may be found there: http://wiki.osll.ru/doku.php?id=etc:users:jcmvbkbc:qemu-target-xtensa
+Linux/xtensa page about [https://wiki.linux-xtensa.org/index.php?title=Xtensa_on_QEMU Xtensa on QEMU].
+[[Category:Completed feature pages]]