ChangeLog/7.1: Difference between revisions

Revision as of 16:29, 21 April 2022

System emulation

Incompatible changes

Consult the 'Removed features' page for details of suggested replacement functionality

New deprecated options and features

Consult the "Deprecated Features" chapter of the QEMU System Emulation User's Guide for further details of the deprecations and their suggested replacements.

68k

Alpha

Arm

The xlnx-zynqmp SoC model now implements the 4 TTC timers
The versal machine now models the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem

AVR

Hexagon

HPPA

Microblaze

MIPS

Nios2

OpenRISC

PowerPC

Renesas RX

Renesas SH

RISC-V

s390x

SPARC

Tricore

x86

Xtensa

Device emulation and assignment

ACPI / SMBIOS

Audio

Block devices

Graphics

I2C

Input devices

IPMI

Multi-process QEMU

Network devices

NVDIMM

NVMe

Emulated NVMe Controller

PCI/PCIe

SCSI

SD card

SMBIOS

TPM

USB

VFIO

virtio

Xen

fw_cfg

9pfs

virtiofs

Semihosting

Audio

Character devices

Crypto subsystem

Authorization subsystem

GUI

GDBStub

TCG Plugins

Host support

Memory backends

Migration

Monitor

QMP

HMP

Network

Block device backends and tools

Tracing

Miscellaneous

User-mode emulation

binfmt_misc

Hexagon

TCG

ARM

Guest agent

Build Information

Python

GIT submodules

Container Based Builds

VM Based Builds

Build Dependencies

Windows

Testing and CI

Known issues

see Planning/7.1

@@ Line 15: / Line 15: @@
 === Arm ===
+* The xlnx-zynqmp SoC model now implements the 4 TTC timers
+* The versal machine now models the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
 === AVR ===