The IBM PS/2 and compatible systems based on the Intel x86 processor.


The i440fx is the motherboard chipset that was popular in the Pentium Pro era. At this point in time, the chipset included both the Northbridge (Memory Controller) and Southbridge (IO devices) functionality.

The i440fx has a PCI 2.1 compatible bus and a PCI-to-ISA bridge. All port I/O and main memory access goes through the i440fx with the exception of access to the local APIC which is part of the processor.

The main interface to the i440fx is the PCI bus. The PCI and Memory Controller (PMC) can be accessed as device 0:0.0 PCI config space. It's a little strange because the PMC is not really a PCI device but duplicates some of the PCI device state.

Memory Layout

Memory entry points. The PMC is responsible for dealing with all memory operations. Read or write accesses to ROM memory is intercepted by the PMC and redirected to the ROM chips. There is still real RAM mapped to these addresses but normally it's left unused (except when using PAM to shadow ROMs).

The normal x86 memory layout looks like:

0x00000 .. 0xA0000      DOS Memory Area       RAM
0xA0000 .. 0xC0000      Video Memory          Device Memory
0xC0000 .. 0xE0000      ISA Extension ROM     ROM
0xE0000 .. 0xF0000      BIOS Extension ROM    ROM
0xF0000 .. 0x100000     BIOS Area             ROM

The DOS Memory Area is just normal RAM. Some areas have special common uses in real mode.

The Video Memory area is used by the Video BIOS and VGA adapter. It maps the VGA and CGA framebuffers and other registers.

The ISA Extension ROM area stores ISA extension ROMs. The BIOS will remap PCI Option ROMs to this space to after PMM. The first 64k of this space is reserved for VGA adapters so normal devices start at 0xC8000.

The BIOS Extension can map either additional ISA ROMs or portions of the BIOS that didn't fit into the normal BIOS Area.

This BIOS Area is the traditional location of the system BIOS. The main requirement is that the very last 16 bytes must be valid as when the system starts out, it jumps to this location to execute the BIOS. Typically, you'll see a trampoline loaded at the very end of the BIOS (at address 0xFFFF0), since the BIOS gets mapped with its end at 0xFFFFF.


The PAM registers make it possible to independently redirect reads and writes in the BIOS ROM area to main memory. The idea is to allow for RAM shadowing which allows read-access for ROMs to come from main memory whereas writes will continue to go to ROMs. This can dramatically improve BIOS execution speed on bare metal because ROM access is generally very slow.

Each PAM register is split into two nibbles. The nibbles then have two reserved bits and then a read-enable and write-enabled bit. Each nibble corresponds to 16k of ROM space except for PAM[0] which refers to 32k.

Build Directions

For 32-bit support:

 ./configure --target-list=i386-softmmu && make

For 64-bit support:

 ./configure --target-list=x86_64-softmmu && make

Suggested Command-Line

 qemu-system-i386 -hda <path to hd image file> -boot c -m 512 -soundhw ac97
 qemu-system-x86_64 -hda <path to hd image file> -boot c -m 512 -soundhw ac97

Supported Guest Operating System


Paolo Bonzini
Richard Henderson
Eduardo Habkost